1. Field of the Invention
The present invention generally relates to methods for testing a semiconductor wafer and, more particularly, to a method for efficiently testing a semiconductor wafer in which reliable electrical contact is ensured between electrodes of semiconductor units and probe pins of a prose.
A semiconductor device is normally manufactured such that a semiconductor wafer with a large number of semiconductor chips, each including at least one semiconductor element, is first produced. For example, a total of 200 to 300 chips may be formed on a wafer. The semiconductor wafer is scribed so that each of the semiconductor chips is packaged. Conventionally, post-packaging tests have been studied more extensively than pre-packaging tests. Recently, however, many semiconductor devices are manufactured such that packaging is conduced in a factory different from the factory where semiconductor wafers are produced. An increasing number of pre-packaged semiconductor wafers are shipped out of factories. For this reason, a growing importance is being attached to a method for testing semiconductor chips on a semiconductor wafer so as to select chips of a satisfactory quality.
2. Description of the Related Art
A description will now be given of a first aspect of a problem inherent in the semiconductor wafer testing method according to the related art.
Generally, each semiconductor chip on a semiconductor wafer is tested such that probe pins of a probe are applied to respective electrodes of individual semiconductor chips. Testing the semiconductor chips of the semiconductor wafer one by one takes a significant period of time, rendering the testing process inefficient. According to one conventional approach to efficiently test the semiconductor chips on the semiconductor wafer, probe pins are applied to respective electrodes of a plurality of semiconductor chips at the same time so that the plurality of semiconductor chips are tested simultaneously.
A probe for testing a plurality of semiconductor chips simultaneously should be provided with several times as many probe pins as the electrodes of a semiconductor chip. Since each pinhead of such probe pins should be applied to the corresponding electrode, the pinheads of the probe pins of a probe are irregularly distributed over a relatively wide area. It is significantly difficult to position the pinheads of all the probe pins with precision. Thus, it is difficult to ensure that the pinheads of all the probe pins are properly applied to the corresponding electrodes when a test is conducted.
Poor reliability in contact between the pinheads of the probe pin and the electrodes on the semiconductor chip results in difficulty in conducting a full-specification test and a burn-in test.
A description will now be given of a second aspect of the problem inherent in the related art.
FIGS. 13 and 14 are a top view and a side view, respectively, showing how a semiconductor wafer is tested according to the related art. Each of a plurality of chips on a wafer is tested using a test probe card and test probe pins adapted for a wafer test.
Referring to FIGS. 13 and 14, each chip 1 on a wafer 2 is provided with permanent pads 7-1 and 7-2. These permanent pads 7-1 and 7-2 are referred to as first electrodes in the description given later in the specification (see, for example, FIG. 20). Each of the permanent pads 7-1 and 7-2 is connected to a various semiconductor circuits that constitute semiconductor elements in the chip 1. The semiconductor elements in the chip 1 are tested by applying test probe pins 6 to the permanent pads 7-1 and 7-2 and supplying an input/output signal and a power source voltage to the semiconductor elements from a test probe card 110.
FIG. 15 is a top view showing how a plurality of chips are tested according to the related art. In the example shown, tae wafer 2 in which the chips 1 are arranged in the X direction and in the Y direction is tested.
In order to test the wafer 2 efficiently and in a short period of time, it is required that the test probe pins 6 be simultaneously applied to the permanent pads 7-1 and 7-2 of the plurality of chips 1 on the wafer 2 so that the plurality of chips 1 are tested at the same time. However, the arrangement of the permanent pads 7-1 and 7-2 is primarily determined by how a subsequent chip assembly process for packaging the chip should be facilitated rather than by how the wafer test should be facilitated. Since the permanent pads 7-1 and 7-2 cannot be removed after the test, various restrictions are imposed on the arrangement and the number of the permanent pads 7-1 and 7-2.
For example, FIG. 15 shows that the permanent pads 7-1 and 7-2 are not arranged at regular intervals in the Y direction. For this reason, the test probe pins 6 at regular intervals can be simultaneously applied to the permanent pads 7-1 and 7-2 only in the X direction. With the arrangement of the permanent pads 7-1 and 7-2 as shown in FIG. 15, only a limited number of chips can be tested simultaneously using the test probe card 110, thus making it difficult to test the wafer 2 efficiently.
Describing the problem in further details, the following restrictions may be imposed when the related art testing method is used to test a plurality of chips on a wafer.
(1) The arrangement of the permanent pads on the plurality of chips on the wafer may also be determined by an arrangement of semiconductor circuits in the chip or positions of lead terminals in a package. For this reason, the arrangement of the permanent pads cannot be determined by how the test should be facilitated.
(2) Pads dedicated to the test may be provided in addition to the permanent pads in order to perform the wafer test efficiently. However, such an addition of test pads increases the chip area.
(3) With the conventional testing method, it is not possible to provide wires across different chips on the wafer.
The following problems arise associated with the above restrictions.
(A) It is difficult to provide a permanent pad arrangement adapted for increasing the number of chips that can be simultaneously tested using a test probe card.
(B) It is necessary to provide various types of test probe cards in the event that chips of different types coexist on the wafer.
(C) It is difficult to connect signal lines in the chip to the test pads dedicated to the test and to directly supply signals to the test pads for the wafer test.
(D) It is necessary to apply test probe pins to all the chips on the wafer to supply the same signal to all the chips on the wafer, when the entirety of the wafer is tested as in a wafer burn-in test.
(E) While it is necessary to provide capacity between a plurality of power sources in order to prevent occurrence of power source noise while the wafer is being tested, by locating the capacity as close as possible to a power supply pad of the permanent pads. However, the testing method according to the related art only enables capacity to be provided at the root of a test probe pin. Accordingly, it has been difficult to reduce the power source noise to a satisfactorily low level.
A description will now be given of a third aspect of the problem inherent in the related art.
FIG. 37 is a top view showing a semiconductor wafer testing method according to the related art.
Referring to FIG. 37, permanent pads 126 are provided on a chip 1. Each of the permanent pads 126 is connected to various circuits in the chip 1. A semiconductor wafer test is performed by applying test probe pins 130 io the permanent pads 126 and applying a voltage and a signal to a plurality of semiconductor elements in the chip 1 via the permanent pads 126. The plurality of semiconductor elements in the chip 1 may be divided into four cell blocks: block A; block B; block C and block D.
The plurality of semiconductor elements are tested by individually testing the cell blocks in the chip. Due to voltage interference or interference caused by capacity coupling that may occur between different cell blocks (for instance, interference may occur between block A and block B), the entirety of the cell blocks should be tested simultaneously for operation. In order to complete a test of a plurality of semiconductor elements in a chip, the time proportional to the nth power of the number of cell blocks (n is a positive integer equal to or greater than 2) is required. An extended period of time is required to detect a defective block. When any of the cell blocks in a chip is found to be defective as a result of the semiconductor wafer test, the chip cannot be shipped as a produce.
Since voltage interference and interference caused by capacity coupling that occurs between different cell blocks in a chip should be considered in the related art test for testing a plurality of semiconductor elements included in the chip, the following problems nay occur.
(1) If any of the cell blocks in a chip is found to be defective, the chip cannot be used as a product.
(2) Since it is necessary to test the entirety of the chips in order to examine voltage interference or the like between different cell blocks in the chip, the time required for the test is all the more extended.
(3) Since the permanent pads are used as test pads, the test pads cannot be located at desired positions.
(4) Since the current status of technology does not allow the size of a test probe pin to be reduced beyond a certain limit (for instance, a diameter of 20 .mu.m), the size of the permanent pad (test pad) to which the test probe pin is applied can be reduced only slightly. Accordingly, it is difficult to provide a large number of permanent pads on the chip.
A description will now be given of a fourth aspect of the problem inherent in the related art.
With the widespread use of semiconductor devices in various electronic appliances, various types of structures of a package accommodating the semiconductor that correspond to the space for mounting the electronic appliances are in use. Accordingly, the semiconductor element accommodated in the semiconductor device should be compatible with the structure of the package.
As a result of using the various types of package structures, different types of packages may be used to accommodate the sane type of semiconductor elements, particularly in the case of general-purpose semiconductor devices.
FIGS. 54 and 55 illustrates the fourth aspect of the related art problem. Referring to FIG. 54, a semiconductor device 211A is a package constructed such that leads 216 extend from shorter sides of a resin package 214A (hereinafter, such a type of resin package will be referred to as a latitudinally elongated package).
Referring to FIG. 55, a semiconductor device 211B is constructed such that leads 216 extend from longer sides of a resin package 214B (hereinafter, such a type of resin package will be referred to as a longitudinally elongated package). A semiconductor element 212A accommodated in the package 214A and a semiconductor element 212B accommodated in the package 214B have the same function.
Subsequently, a description will now be given, with reference to FIGS. 56 and 57, of how the semiconductor elements 212A and 212B are connected to the leads 216.
FIG. 56 shows how the semiconductor element 212A in the latitudinally elongated package 214A is connected to the lead 216. As shown in FIG. 56, the semiconductor element 212A should be provided to adapt to the latitudinally elongated configuration of the package 214A.
Electrodes 218A formed in the semiconductor element 212A are electrically connected to the respective leads 216 via wires 219. The wires 219 should be as short as possible in order to control the loss. Therefore, in the conventional package 214A, the electrodes 218A are often provided along the shorter sides of the semiconductor element 212B.
FIG. 57 shows how the semiconductor element 212B in the longitudinally elongated package 214B is connected to the leads 216. As shown in FIG. 57, the semiconductor element 212B should be provided to adapt to the longitudinally elongated configuration of the package 214B.
Electrodes 218B formed in the semiconductor element 212B aria electrically connected to the respective leads 216 via wires 219. The wires 219 should be as short as possible in order to control the loss. Therefore, in the conventional package 214B, the electrodes 218B are often provided along the longer sides of the semiconductor element 212B.
As described above, the semiconductor device 212A as shown in FIGS. 54 and 56 and the semiconductor device 212B as shown in FIGS. 55 and 57 are of the same function. However, the electrodes 218A and 218B are provided in different arrangements in the semiconductor device 212A and in the semiconductor device 212B. Thus, the related art has a drawback in that the semiconductor element 212A and 212B have to be produced independently due only to the different arrangements of the electrodes 218A and 218B.
In addition, the following problem is inherent in inventory management of the semiconductor devices produced according to the related art. In order to deliver semiconductor products in a short period of time in response a client order that could be expected at any moment, there has to be a corresponding volume of stock capable of producing a corresponding amount of semiconductor elements. According to the related art whereby semiconductor elements of different electrode arrangements are accommodated in packages of different structures, if the stock is prepared based on a wrong prospective order, inventory of an improper scale or a defective inventory results. For this reason, according to the related art, determination of the prospect order is such a difficult task that inventory management has become difficult.
One approach to the aforementioned drawback of the related art is to provide both the electrodes for the latitudinally elongated package and the electrodes for the longitudinally elongated package on the semiconductor element.
However, providing the electrodes for the latitudinally elongated package and the electrodes for the longitudinally elongated package on the same surface of the semiconductor element results in twice the number of electrodes as compared with the semiconductor elements 212A and 212B. Accordingly, the space required to accommodate the electrodes increases so that the semiconductor element become excessively large in scale.